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FPGA Implementations of Neural Networks

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Main Data

Author:	Amos R. Omondi, Jagath C. Rajapakse
Editor:	Amos R. Omondi, Jagath C. Rajapakse
Title:	FPGA Implementations of Neural Networks
Publisher:	Springer-Verlag
ISBN/ISSN:	9780387284873
Edition:	1
Price:	CHF 184.80
Publication date:	01/01/2006

Content

Category:	Informatik, EDV Buch
Language:	English

Technical Data

Pages:	360
Kopierschutz:	DRM
Geräte:	PC/MAC/eReader/Tablet
Formate:	PDF

Table of contents

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

Table of contents

	Contents	5
	Preface	9
	FPGA NEUROCOMPUTERS	13
	1.1 Introduction	13
	1.2 Review of neural-network basics	15
	1.3 ASIC vs. FPGA neurocomputers	21
	1.4 Parallelism in neural networks	24
	1.5 Xilinx Virtex-4 FPGA	25
	1.6 Arithmetic	27
	1.7 Activation-function implementation: unipolar sigmoid	33
	1.8 Performance evaluation	44
	1.9 Conclusions	46
	References	46
	ON THE ARITHMETIC PRECISION FOR IMPLEMENTING BACK- PROPAGATION NETWORKS ON FPGA: A CASE STUDY	49
	2.1 Introduction	49
	2.2 Background	51
	2.3 Architecture design and implementation	55
	2.4 Experiments using logical-XOR problem	60
	2.5 Results and discussion	62
	2.6 Conclusions	67
	References	68
	FPNA: CONCEPTS AND PROPERTIES	74
	3.1 Introduction	74
	3.2 Choosing FPGAs	76
	3.3 FPNAs, FPNNs	82
	3.4 Correctness	97
	3.5 Underparameterized convolutions by FPNNs	99
	3.6 Conclusions	107
	References	108
	FPNA: APPLICATIONS AND IMPLEMENTATIONS	113
	Introduction	113
	4.1 Summary of Chapter 3	114
	4.2 Towards simplified architectures: symmetric boolean functions by FPNAs	115
	4.3 Benchmark applications	119
	4.4 Other applications	123
	4.5 General FPGA implementation	126
	4.6 Synchronous FPNNs	130
	4.7 Implementations of synchronous FPNNs	134
	4.8 Implementation performances	140
	4.9 Conclusions	143
	References	144
	BACK-PROPAGATION ALGORITHM ACHIEVING 5 GOPS ON THE VIRTEX-E	147
	5.1 Introduction	148
	5.2 Problem specification	149
	5.3 Systolic implementation of matrix-vector multiply	151
	5.4 Pipelined back-propagation architecture	152
	5.5 Implementation	154
	5.6 MMAlpha design environment	157
	5.7 Architecture derivation	159
	5.8 Hardware generation	165
	5.9 Performance evaluation	167
	5.10 Related work	169
	5.11 Conclusion	170
	Appendix	171
	References	173
	FPGA IMPLEMENTATION OF VERY LARGE ASSOCIATIVE MEMORIES	176
	6.1 Introduction	176
	6.2 Associative memory	177
	6.3 PC Performance Evaluation	188
	6.4 FPGA Implementation	193
	6.5 Performance comparisons	199
	6.6 Summary and conclusions	201
	References	202
	FPGA IMPLEMENTATIONS OF NEOCOGNITRONS	205
	7.1 Introduction	205
	7.2 Neocognitron	206
	7.3 Alternative neocognitron	209
	7.4 Reconfigurable computer	213
	7.5 Reconfigurable orthogonal memory multiprocessor	214
	7.6 Alternative neocognitron hardware implementation	217
	7.7 Performance analysis	223
	7.8 Applications	226
	7.9 Conclusions	229
	References	230
	SELF ORGANIZING FEATURE MAP FOR COLOR QUANTIZATION ON FPGA	233
	8.1 Introduction	233
	8.2 Algorithmic adjustment	236
	8.3 Architecture	239
	8.4 Implementation	243
	8.5 Experimental results	247
	8.6 Conclusions	250
	References	250
	IMPLEMENTATION OF SELF-ORGANIZING FEATURE MAPS IN RECONFIGURABLE HARDWARE	254
	9.1 Introduction	254
	9.2 Using reconfigurable hardware for neural networks	255
	9.3 The dynamically reconfigurable rapid prototyping system RAPTOR2000	257
	9.4 Implementing self-organizing feature maps on RAPTOR2000	259
	9.5 Conclusions	274
	References	274
	FPGA IMPLEMENTATION OF A FULLY AND PARTIALLY CONNECTED MLP	277
	10.1 Introduction	277
	10.2 MLP/XMLP and speech recognition	279
	10.3 Activation functions and discretization problem	282
	10.4 Hardware implementations of MLP	290
	10.5 Hardware implementations of XMLP	297
	10.6 Conclusions	299
	Acknowledgments	300
	References	301
	FPGA IMPLEMENTATION OF NON-LINEAR PREDICTORS	303
	11.1 Introduction	304
	11.2 Pipeline and back-propagation algorithm	305
	11.3 Synthesis and FPGAs	310
	11.4 Implementation on FPGA	319
	11.5 Conclusions	325
	References	327
	THE REMAP RECONFIGURABLE ARCHITECTURE: A RETROSPECTIVE	330
	12.1 Introduction	331
	12.2 Target Application Area	332
	12.3 REMAP-ß design and implementation	340
	12.4 Neural networks mapped on REMAP-ß	351
	12.5 REMAP- . architecture	358
	12.6 Discussion	359
	12.7 Conclusions	362
	Acknowledgments	362
	References	362