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Autor: Amos R. Omondi, Jagath C. Rajapakse
Herausgeber: Amos R. Omondi, Jagath C. Rajapakse
Titel: FPGA Implementations of Neural Networks
Verlag: Springer-Verlag
ISBN/ISSN: 9780387284873
Auflage: 1
Preis : CHF 184.80
Erscheinungsdatum:
Inhalt
Kategorie: Informatik, EDV Buch
Sprache: English
Technische Daten
Seiten: 360
Kopierschutz: DRM
Geräte: PC/MAC/eReader/Tablet
Formate: PDF
Inhaltsangabe
During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.
Inhaltsverzeichnis
Contents5
Preface9
FPGA NEUROCOMPUTERS13
1.1 Introduction13
1.2 Review of neural-network basics15
1.3 ASIC vs. FPGA neurocomputers21
1.4 Parallelism in neural networks24
1.5 Xilinx Virtex-4 FPGA25
1.6 Arithmetic27
1.7 Activation-function implementation: unipolar sigmoid33
1.8 Performance evaluation44
1.9 Conclusions46
References46
ON THE ARITHMETIC PRECISION FOR IMPLEMENTING BACK- PROPAGATION NETWORKS ON FPGA: A CASE STUDY49
2.1 Introduction49
2.2 Background51
2.3 Architecture design and implementation55
2.4 Experiments using logical-XOR problem60
2.5 Results and discussion62
2.6 Conclusions67
References68
FPNA: CONCEPTS AND PROPERTIES74
3.1 Introduction74
3.2 Choosing FPGAs76
3.3 FPNAs, FPNNs82
3.4 Correctness97
3.5 Underparameterized convolutions by FPNNs99
3.6 Conclusions107
References108
FPNA: APPLICATIONS AND IMPLEMENTATIONS113
Introduction113
4.1 Summary of Chapter 3114
4.2 Towards simplified architectures: symmetric boolean functions by FPNAs115
4.3 Benchmark applications119
4.4 Other applications123
4.5 General FPGA implementation126
4.6 Synchronous FPNNs130
4.7 Implementations of synchronous FPNNs134
4.8 Implementation performances140
4.9 Conclusions143
References144
BACK-PROPAGATION ALGORITHM ACHIEVING 5 GOPS ON THE VIRTEX-E147
5.1 Introduction148
5.2 Problem specification149
5.3 Systolic implementation of matrix-vector multiply151
5.4 Pipelined back-propagation architecture152
5.5 Implementation154
5.6 MMAlpha design environment157
5.7 Architecture derivation159
5.8 Hardware generation165
5.9 Performance evaluation167
5.10 Related work169
5.11 Conclusion170
Appendix171
References173
FPGA IMPLEMENTATION OF VERY LARGE ASSOCIATIVE MEMORIES176
6.1 Introduction176
6.2 Associative memory177
6.3 PC Performance Evaluation188
6.4 FPGA Implementation193
6.5 Performance comparisons199
6.6 Summary and conclusions201
References202
FPGA IMPLEMENTATIONS OF NEOCOGNITRONS205
7.1 Introduction205
7.2 Neocognitron206
7.3 Alternative neocognitron209
7.4 Reconfigurable computer213
7.5 Reconfigurable orthogonal memory multiprocessor214
7.6 Alternative neocognitron hardware implementation217
7.7 Performance analysis223
7.8 Applications226
7.9 Conclusions229
References230
SELF ORGANIZING FEATURE MAP FOR COLOR QUANTIZATION ON FPGA233
8.1 Introduction233
8.2 Algorithmic adjustment236
8.3 Architecture239
8.4 Implementation243
8.5 Experimental results247
8.6 Conclusions250
References250
IMPLEMENTATION OF SELF-ORGANIZING FEATURE MAPS IN RECONFIGURABLE HARDWARE254
9.1 Introduction254
9.2 Using reconfigurable hardware for neural networks255
9.3 The dynamically reconfigurable rapid prototyping system RAPTOR2000257
9.4 Implementing self-organizing feature maps on RAPTOR2000259
9.5 Conclusions274
References274
FPGA IMPLEMENTATION OF A FULLY AND PARTIALLY CONNECTED MLP277
10.1 Introduction277
10.2 MLP/XMLP and speech recognition279
10.3 Activation functions and discretization problem282
10.4 Hardware implementations of MLP290
10.5 Hardware implementations of XMLP297
10.6 Conclusions299
Acknowledgments300
References301
FPGA IMPLEMENTATION OF NON-LINEAR PREDICTORS303
11.1 Introduction304
11.2 Pipeline and back-propagation algorithm 305
11.3 Synthesis and FPGAs 310
11.4 Implementation on FPGA319
11.5 Conclusions325
References327
THE REMAP RECONFIGURABLE ARCHITECTURE: A RETROSPECTIVE330
12.1 Introduction331
12.2 Target Application Area332
12.3 REMAP-ß  design and implementation340
12.4 Neural networks mapped on REMAP-ß351
12.5 REMAP- . architecture358
12.6 Discussion359
12.7 Conclusions362
Acknowledgments362
References362